It is known in the art to form lateral PNP transistors substantially concurrently with, and using processes compatible with, vertical NPN transistors. Due primarily to previous lithographic limitations, however, these lateral PNP transistors were fabricated with undesirably wide base widths, and exhibited poor operating characteristics relative to the vertical NPN transistors. The wide base widths typically resulted in lateral PNP transistors having poor frequency response, and low beta-gain.
Recent advances in lithographic technology now permit the fabrication of lateral PNP devices having sub-micron width base regions. However, these lateral transistors are typically formed on a low concentration N- epitaxial layer, the epitaxial layer concentration being dictated by the vertical NPN transistor requirements. As the base widths of the lateral PNP transistors are decreased in accordance with lithographic technology to improve frequency response and increase beta-gain, the low epitaxial layer concentration results in the problems of PFET collector current leakage, base current leakage, and emitter-collector punch-through.
IBM Technical Disclosure Bulletin, Vol. 13, No. 6, page 1457, November 1970, shows a method of fabricating a lateral PNP transistor wherein an N type diffusion is performed in an N- type epitaxial region before emitter and collector regions are formed. The emitter and collector regions are diffused into the N diffused epitaxial region so as to form a graded base region there-between.
U.S. Pat. No. 4,510,676 to Anantha et al., assigned to the assignee of the present invention, shows a method of forming a lateral PNP transistor on an integrated circuit with and in a process compatible with the formation of a vertical NPN transistor.
IBM Technical Disclosure Bulletin, Vol. 22, No. 7, pgs. 2939-2942, December 1979, shows a method of forming a lateral PNP transistor structure wherein a silicon dioxide sidewall is used as a mask to form a thin base region. The sidewall is grown over the edge of a doped polysilicon layer. One electrode is formed by out-diffusion from the polysilicon layer into an underlying epitaxial region. The second electrode is formed by implantation, diffusion, or out-diffusion into the epitaxial region using the sidewall as a mask.
U.S. Pat. No. 4,005,451 to Martinelli et al. shows a lateral transistor wherein the collector and emitter region configurations and doping profiles are selected to promote current flow at a location spaced away from the device surface.
U.S. Pat. No. 4,283,236 to Sirsi is exemplary of "double-diffused" type lateral transistors, showing a lateraI PNP transistor formed in an N- epitaxial region and having base and emitter regions both diffused through the same aperture. The region between the emitter and collector diffusions is counter-doped with a P type ion implant.